AFE58JD32ZBV

AFE58JD32ZBV屬性

---

AFE58JD32ZBV描述

The AFE58JD32 device is a highly-integrated, analog front-end solution specifically designed for ultrasound systems where high performance, low power, and small size are required.
The AFE58JD32 is an integrated analog front-end (AFE) optimized for medical ultrasound application. The device is realized through a multichip module (MCM) with three dies: two voltage-controlled amplifier (VCA) dies and one analog-to-digital converter (ADC) die. Each VCA die has 16 channels and the ADC die converts all of the 32 channels.
Each channel in the VCA die is configured in either of two modes: time gain compensation (TGC) mode or continuous wave (CW) mode. In TGC mode, each channel includes an input attenuator (ATTEN), a low-noise amplifier (LNA) with variable-gain, and a third-order, low-pass filter (LPF). The attenuator supports an attenuation range of 8 dB to 0 dB, and the LNA supports gain ranges from 20 dB to 51 dB. The LPF cutoff frequency can be configured at 5 MHz, 7.5 MHz, 10 MHz, or 12.5 MHz to support ultrasound applications with different frequencies. In CW mode, each channel includes an LNA with a fixed gain of 18 dB, and a low-power passive mixer with 16 selectable phase delays. Different phase delays can be applied to each analog input signal to perform an on-chip beamforming operation. A harmonic filter in the CW mixer suppresses the third and fifth harmonic to enhance the sensitivity of the CW Doppler measurement.
The ADC die has 16 physical ADCs. Each ADC converts two sets of outputs – one from each VCA die. The ADC is configured to operate with a resolution of 12 bits or 10 bits. The ADC resolution can be traded off with conversion rate, and operates at maximum speeds of 80 MSPS and 100 MSPS at 12-bit and 10-bit resolution, respectively. The ADC is designed to scale its power with sampling rate. The output interface of the ADC comes out through a low-voltage differential signaling (LVDS) which can easily interface with low-cost field-programmable gate arrays (FPGAs).
The AFE58JD32 includes an optional digital demodulator and JESD204B data packing blocks. The digital in-phase and quadrature (I/Q) demodulator with programmable decimation filters accelerates computationally-intensive algorithms at low power. The device also supports an optional JESD204B interface that runs up to 5-Gbps and further reduces the circuit-board routing challenges in high-channel count systems.
聯系人：Luna 何小姐 朱先生【只只原裝 片片原廠】地 址：廣東深圳市福田區華強北上步工業區204棟東座516【微信號:13410068358】郵 編：518000 電 話：0755-82548684 13410068358【代傳 真：0755-82523504【每一片都來自原廠原裝可追溯】郵 箱：1779939071@qq.com
深圳市燁弘軒電子有限公司 為一般納稅人 可開具17%增值稅票 有合作基礎可申請月結，延長賬期等多種供貨付款方式。
公司經營目標：整合全球資源全 芯 全意為您服務。
公司服務宗旨：客戶虐我千百遍，我待客戶如初戀。

---

AFE58JD32ZBV相關產品