LMK04616ZCRR

LMK04616ZCRR屬性

---

LMK04616ZCRR描述

Dual Loop PLL Architecture
65-fs RMS Jitter (10 kHz to 20 MHz)
85-fs RMS Jitter (100 Hz to 20 MHz)
–165-dBc/Hz Noise Floor at 122.88 MHz
JESD204B Support
Single Shot, Pulsed, and Continuous SYSREF
16 Differential Output Clocks in 8 Frequency Groups
Digital Delay (DDLY) of ½ × Clock Distribution Path Frequency (2 GHz Maximum)
Programmable Output Swing Between 700 mVpp to 1600 mVpp
Each Output Pair Can be Configured to SYSREF Clock Output
16-Bit Channel Divider
Minimum SYSREF Frequency of 25 kHz
Maximum Output Frequency of 2 GHz
Precision Digital Delay, Dynamically Adjustable
60-ps Step Analog Delay
50% Duty Cycle Output Divides, 1 to 65535
(Even and Odd)
4 Reference Inputs
Holdover Mode, When Inputs are Lost
Automatic and Manual Switch-Over Modes
Loss-of-Signal (LOS) Detection
1.05-W Typical Power Consumption With 16 Outputs Active
Operates Typically From a 1.8-V (Outputs, Inputs) and 3.3-V Supply (Digital, PLL1, PLL2_OSC, PLL2 Core)
Fully Integrated Programmable Loop Filter
PLL2
PLL2 Phase Detector Rate Up to 250 MHz
OSCin Frequency-Doubler
Integrated Low-Noise VCO
Internal Power Conditioning: Better Than –80dBc PSRR on VDDO for 122.88-MHz Differential Outputs
3- or 4-Wire SPI Interface (4-Wire is Default)
–40oC to +85oC Industrial Ambient Temperature
Supports 105oC PCB Temperature (Measured at Thermal Pad)
LMK04616: 10-mm × 10-mm NFBGA-144 Package With 0.8-mm Pitch
聯系人：Luna 何小姐 朱先生【只只原裝 片片原廠】地 址：廣東深圳市福田區華強北上步工業區204棟東座516【微信號:13410068358】郵 編：518000 電 話：0755-82548684 13410068358【代傳 真：0755-82523504【每一片都來自原廠原裝可追溯】郵 箱：1779939071@qq.com
深圳市燁弘軒電子有限公司 為一般納稅人 可開具17%增值稅票 有合作基礎可申請月結，延長賬期等多種供貨付款方式。
公司經營目標：整合全球資源全 芯 全意為您服務。
公司服務宗旨：客戶虐我千百遍，我待客戶如初戀。

---

LMK04616ZCRR相關產品