AFE58JD32LP

AFE58JD32LP屬性

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AFE58JD32LP描述

描述
The AFE58JD32LP is a highly integrated, analog front-end (AFE) solution specifically designed for portable ultrasound systems where high performance, low power, and small size are required.

The device is realized through a multichip module (MCM) with two dies: 1 VCA die and 1 ADC die. The VCA die has 32 channels that interface with the 16 channels of the ADC die. Each ADC channel alternately converts an odd and an even VCA channel.

Each channel in the VCA die can be configured in either of two modes: time-gain-compensation (TGC) mode or continuous wave (CW) mode. In the TGC mode, each channel includes a low-noise amplifier (LNA), a programmable attenuator (ATTEN), a programmable gain amplifier and a third-order, low-pass filter (LPF). The LNA gain is programmable to 21 dB, 18 dB, or 15 dB. The ATTEN supports an attenuation range of 0 dB to 36 dB, with digital control for the attenuation. The PGA provides gain options from 21 dB to 27 dB in steps of 3 dB. The LPF cutoff frequency can be set between 10 MHz and 25 MHz to support ultrasound applications with different frequencies. In the CW mode, the output of the LNA goes to a low-power passive mixer with 16 selectable phase delays. Different phase delays can be applied to each analog input signal to perform an on-chip beamforming operation. A harmonic filter in the CW mixer suppresses the third and fifth harmonic to enhance the sensitivity of the CW Doppler measurement.

The 16 channels of the ADC die can be configured to operate with a resolution of 12 bits or 10 bits. The ADC resolution can be traded off with conversion rate and can operate at maximum speeds of 80 MSPS and 100 MSPS at 12-bit and 10-bit resolution, respectively. Because each ADC alternately converts two VCA channels, the resulting maximum sample rate of each of the 32 channels of the AFE is 40 MSPS and 50 MSPS in the 12-bit and 10-bit modes, respectively. The ADC is designed to scale its power with sampling rate. The output interface of the ADC comes out through a low-voltage differential signaling (LVDS), which can easily interface with low-cost field-programmable gate arrays (FPGAs).

A very low-power AFE solution makes it suitable for system with strict battery-life requirement.

The AFE is available in a 15 mm × 15 mm 289-pin NFBGA package and is pin-compatible with the AFE5832 family.
特性
32-Channel AFE for Ultrasound Applications:
LNA, Attenuator, LPF, ADC, CW Mixer, and Digital I/Q Demodulator
Digital Time Gain Compensation (DTGC)
Total Gain Range: 0 dB to 48 dB
Low-Noise Amplifier (LNA) With Programmable Gain:
Low Current Noise of 1pA/rtHz
Gain: 21 dB, 18 dB, and 15 dB
Linear Input Range: up to 700 mVPP
Programmable Attenuator (ATTEN):
Attenuation Range (Steps of 0.125 dB):
0 to 36 dB
Digital TGC Engine
Programmable Gain Amplifier (PGA):
Gain: 21 dB, 24 dB, and 27 dB
Third-Order, Linear-Phase, Low-Pass Filter (LPF):
Cut-off Frequency From 10 MHz to 25 MHz
16 ADCs Converting at 12-Bit, 80 MSPS or 10-Bit, 100 MSPS:
Each ADC Converts Two Sets of Inputs at Half Rate
12-Bit Mode: 72-dBFS SNR
10-Bit Mode: 61-dBFS SNR
TGC Mode Power w/o digital I/Q Demodulator:
Lowest Power of 18.5 mW/Ch in Low Power Mode, 4 nV/rtHz, 10-Bit, 20 MSPS, LVDS (2x rate)
27.8 mW/Ch at 3 nV/rtHz in Low Noise Mode at 12-Bit, 40 MSPS
24.4 mW/Ch at 4 nV/rtHz in Low Power Mode at 12-Bit, 40 MSPS
Excellent Device-to-Device Gain Matching:
±0.5 dB (Typical)
Harmonic Distortion: –55 dBc level
Fast and Consistent Overload Recovery
Continuous Wave (CW) Path With:
Low Close-In Phase Noise of –148 dBc/Hz at 1-kHz Frequency Offset off 5-MHz Carrier
Power Consumption w/o Signal: 10 mW/Ch
Phase Resolution: λ/16
12-dB Suppression on Third and Fifth Harmonics
Digital I/Q demodulator:
Decimation Filter M = 1 to 63
Data Throughput Reduction After Decimation
On-Chip RAM with 32 Preset Profiles
LVDS Interface with a Speed Up to 1-Gbps
Small Package: 15-mm × 15-mm NFBGA-289
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