MC12013P
MC12013P屬性
- 0
MC12013P描述
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This device is a two–modulus prescaler which will divide by 10
and 11. A MECL–to–MTTL translator is provided to interface
directly with the MC12014 Counter Control Logic. In addition,
there is a buffered clock input and MECL bias voltage source.
• 550 MHz (÷10/11)
• MECL to MTTL Translator on Chip
• MECL and MTTL Enable Inputs
• 5.0 or –5.2 V Operation*
• Buffered Clock Input — Series Input RC Typ, 20 Ω and 4.0 pF
• VBB Reference Voltage
• 310 Milliwatts (Typ)
* When using a 5.0 V supply, apply 5.0 V to Pin 1
(VCCO), Pin 6 (MTTL VCC), Pin 16 (VCC), and ground
Pin 8 (VEE). When using –5.2 V supply, ground Pin 1
(VCCO), Pin 6 (MTTL VCC), and Pin 16 (VCC) and apply
–5.2 V to Pin 8 (VEE). If the translator is not required, Pin
6 may be left open to conserve DC power drain.