latticeecp3主要特性:

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BTS5589G

C40273

LT1469CDF

K6X0808X1D-DF70

half 36x36, two 18x18 or four 9x9 multipliers

advanced 18x36 mac and 18x18 multiply-multiply-accumulate (mmac) operations

adc/dac, 7:1 lvds, xgmii

high speed adc/dac devices higher logic density for increased system integration

• 17k to 149k luts

• 133 to 586 i/os embedded serdes

• 150 mbps to 3.2 gbps for generic 8b10b, 10-bit serdes, and 8-bit serdes modes

• data rates 230 mbps to 3.2 gbps per channel for all other protocols

• up to 16 channels per device: pci express, sonet/sdh, ethernet (1gbe, sgmii, xaui), cpri, smpte 3g and serial rapidio sysdsp™

• fully cascadable slice architecture

• 12 to 160 slices for high performance multiply and accumulate

• powerful 54-bit alu operations

• time division multiplexing mac sharing

• rounding and truncation

• each slice supports flexible memory resources

• up to 6.85mbits sysmem™ embedded block ram (ebr)

• 36k to 303k bits distributed ram sysclock analog plls and dlls

• two dlls and up to ten plls per device pre-engineered source synchronous i/o

• ddr registers in i/o cells

• dedicated read/write levelling functionality

• dedicated gearing logic

• source synchronous standards support

• dedicated ddr/ddr2/ddr3 memory with dqs support

• optional inter-symbol interference (isi) correction on outputs programmable sysi/o™ buffer supports wide range of interfaces

• on-chip termination

• optional equalization filter on inputs

• lvttl and lvcmos 33/25/18/15/12

• sstl 33/25/18/15 i, ii

• hstl15 i and hstl18 i, ii

• pci and differential hstl, sstl

• lvds, bus-lvds, lvpecl, rsds, mlvds 

flexible device configuration

• dedicated bank for configuration i/os

• spi boot flash interface

• dual-boot images supported

• slave spi

• transfr™ i/o for simple field updates

• soft error detect embedded macro

system level support

• ieee 1149.1 and ieee 1532 compliant

• reveal logic analyzer

• orcastra fpga configuration utility

• on-chip oscillator for initialization & general use

• 1.2v core power supply

表1.latticeecp3系列產品性能表


圖1.latticeecp3-35簡化方框圖(頂層)

latticeecp3串行協議評估板

the latticeecp3 serial protocol evaluation board allows designers to investigate and experiment with the features of the latticeecp3 high-speed serdes transceivers. it is available for full and detailed characterization of the high speed i/o channels and includes interfaces for some of the latest protocol interconnections.

the latticeecp3 serial protocol evaluation board allows designers to investigate and experiment with the features of the latticeecp3 high-speed serdes transceivers. it is available for full and detailed characterization of the high speed i/o channels and includes interfaces for some of the latest protocol interconnections.

latticeecp3串行協議評估板主要特性:

pci express x4 edge connector interfaces

allow demonstration of pci express (x4) interfaces

this board is larger than the standard pcie form-factor, but will demonstrate pcie x4 functionality with an open-frame motherboard

allow control of serdes pcs registers using the serial client interface (orcastra)

serial ata interfaces for host and target configurations

rj45 interface to 10/100/1000 ethernet

on-board boot flash.

64m serial spi flash

parallel flash via machxo™ crossover pld programming bridge

switches, leds, displays for demo purposes

several debug and analysis connections

input connection for lab-power supply

power connections and power sources

ispvm™ programming support

on-board and external reference clock sources

圖2.latticeecp3串行協議評估板外形圖

圖3.latticeecp3串行協議評估板電路圖(1)

圖4.latticeecp3串行協議評估板電路圖(2)

圖5.latticeecp3串行協議評估板電路圖(3)

圖6.latticeecp3串行協議評估板電路圖(4)

圖7.latticeecp3串行協議評估板電路圖(5)

圖8.latticeecp3串行協議評估板電路圖(6)

圖9.latticeecp3串行協議評估板電路圖(7)

圖10.latticeecp3串行協議評估板電路圖(8)

圖11.latticeecp3串行協議評估板電路圖(9)

圖12.latticeecp3串行協議評估板電路圖(10)

圖13.latticeecp3串行協議評估板電路圖(11)

圖14.latticeecp3串行協議評估板電路圖(12)

圖15.latticeecp3串行協議評估板電路圖(13)

圖16.latticeecp3串行協議評估板電路圖(14)

圖17.latticeecp3串行協議評估板電路圖(15)
latticeecp3串行協議評估板材料清單(bom):






lattice 公司的latticeecp3是第三代大容量具有serdes功能的fpga,提供多協議和xayu抖動兼容的3.2g serdes,ddr3存儲器接口,功能強大的dsp功能,高密度的片上存儲器以及多達149k的luts和多達586個用戶i/o,非常適合用在大兩的對成本和功耗敏感的有線和無線基礎設備.而latticeecp3串行協議評估板則可用于ddr2存儲器接口,pci express和吉比特以太網.介紹了latticeecp3主要特性,方框圖,以及latticeecp3串行協議評估板主要特性,完整的電路圖和材料清單(bom).