VR行業興起于15年，繁盛于16年。至今已經淘汰很多VR企業。能夠在這股風尖浪潮上存活下來的企業，定是具有強大的經濟后盾，或者占據了強大的市場份額。然而，能夠在這股浪潮上頂風而上，更是值得欽佩。
16年淘汰很多的VR商家，見證了優勝劣汰的局面。17年也有很多商家蠢蠢欲動，但都不敢下手。每一個行業都有一個行業的生存規律，優勝劣汰。
VR是怎么實現現實與虛擬的超越呢，在有限的空間，實現無限的想象！在有限的空間建立一個無限的虛擬世界。VR實現了人們的穿越夢想，回到過去，或者回到未來。都是一種通過虛擬的空間實現。
TC358870XBG作為VR的一個不可缺少的元件，實現圖像的轉換與實現圖像縮小與放大。從而建立一個虛擬世界。TC358870XBG的完整打板資料以及免費的技術支持，請咨詢客服QQ 1242388708或者電聯18201635651 Mandy。
一下是TC358870XBG的一些詳細參數。
Features
● HDMI-RX Interface
HDMI 1.4b
- Video Formats Support (Up to 4K×2K / 30fps), maximum 24 bps (bit-per-pixel) no deep color support
RGB, YCbCr444: 24-bpp
YCbCr422: 24-bpp
- Color Conversion
4:2:2 to 4:4:4 is supported
4:4:4: to 4:2:2 is supported
RGB888 to YCbCr (4:4:4 / 4:2:2) is supported
YCbCr (4:4:4 / 4:2:2) to RGB888/666 is supported
Note: for RGB666 (R=R[5:0],2'b00, G=G[5:0],2'b00, B=G[5:0],2'b00)
- Maximum HDMI clock speed: 297 MHz
- Audio Supports
Internal Audio PLL to track N/CTS value transmitted by the ACR packet.
- 3D Support
- Support HDCP1.4 decryptions
- EDID Support, Release A, Revision 1 (Feb 9, 2000)
First 128 byte (EDID 1.3 structure)
First E-EDID Extension: 128 bytes of CEA Extension version 3 (specified in CEA-861-D)
Embedded 1K-byte SRAM (EDID_SRAM)
Does not support Audio Return Path and HDMI Ethernet Channels
● DSI TX Interface
MIPI DSI compliant (Version 1.1 22 November 2011)
Dual links DSI (DSI0 and DSI1), each link supports 4 data lanes @1 Gbps/ data lane
- DSI0 carries the left half data of HDMI Rx video stream and DSI1 carries the right one at the default configuration.
- Left or right data can be assigned/programmed to either DSI Tx link
- The maximum length of each half is limited to
2048-pixel plus up to full length overlap, DSI0 data length could be different from that of DSI1's
- The maximum Hsync skew between DSI0 and DSI1 can be less than 10 ByteClk
Single link DSI, maximum horizontal pixel width
- 2558 pixels (24-bit per pixel)
- 3411 pixels (16-bit per pixel)
Supports video data formats
- RGB666, RGB888, YCbCr444, YCbCr 422 16-bit and YCbCr 422 24-bit
- YCbCr inputs can be converted into RGB before outputting
● I2C Interface
Support for normal (100 kHz), fast mode (400 kHz) and ultrafast mode (2 MHz)
Slave Mode
- To be used by an external Master to configure all TC358870XBG internal registers, including EDID_SRAM and panel control
- Support 2 I2C Slave Addresses (0x0F & 0x1F) selected through boot-strap pin (INT)
● Audio Output Interface
Up to four I2S data lines for supporting multi-Channel audio data (5.1 and 7.1)
Maximum audio sample frequency supported is 192 kHz @8 CH
Support 16, 18, 20 or 24-bit data (depend on HDMI input stream)
Support Master Clock output only
Support 32 bit-wide time-slot only
Output Audio Over Sampling clock (256fs)
Either I2S or TDM Audio interface available (pins are multiplexed)
I2S Audio Interface
- Support Left or Right-justify with MSB first
TDM (Time Division Multiplexed) Audio Interface
- Fixed to 8 channels (depend on HDMI input stream)
P-VFBGA80-0707-0.65-001
Weight: 67.1 mg (Typ.)
TC358870XBG
TC358870XBG
#
TITLE DESCRIPTION
1 2 3 4 5 6 7 8
COVER PAGE ︵THIS PAGE︶
UH2C/D
- MAIN
HDMI
SECTION
MIPI
SECTION
AUDIO
I2S,
IR
CONTROL ︵
I2C/
CLOCK/
RESET/
TEST︶
POWER SECTION
CHANGES/BLOCK DIAGRAM
與TC358870XBG同一個系列的橋接芯片還有TC358860XBG，TC358779XBG，TC358749XBG，TC358775XBG等，更多資料請詳詢客服或者電聯15910392822王小姐. 免費的技術支持以及全程的跟進，讓您快速完成調試。盡快生產。
